1. Field of the Invention
This invention relates to technology for remote debugging by utilizing programs executed on a target device, and more specifically relates to technology for debugging by utilizing an on-chip debug emulator.
2. Description of Related Art
The full-function in-circuit emulator (hereafter called full ICE) and the on-chip debug emulator (hereafter called OCD) are known in the art as emulators for remotely debugging programs executed on the target device.
When using full ICE, a target device made up of a target board with a socket connecting to the full ICE is mounted in place of the microcomputer. During debugging, the full ICE is connected to the target board instead of the microcomputer. An emulator chip for emulating CPU functions built into the full ICE or peripheral emulator chips for emulating peripheral functions then emulate (simulate) the microcomputer operation based on commands from a host device such as a debugger on a personal computer. Debug circuits are formed inside and outside the emulator chip in the full ICE, and a probe cable for transferring all signals used by the target device microcomputer is connected to the target board and the full Ice.
The full ICE provides a full range of debugging functions using debug circuits both inside and outside the emulator chip, and can debug nearly all the terminals on the microcomputer. However the full ICE is expensive and must be designed to match the individual microcomputer. Moreover the emulation is performed by the emulator chip so the operation may differ from that of the actual microcomputer.
In the case of the OCD, the debug circuits are in the microcomputer itself in the target device. The OCD connects to the debug circuits within the microcomputer on the target device by way of a debug interface (I/F) and data for commands from the host device are transferred to and from the microcomputer. A dedicated connector for connecting to the OCD is installed on the target device.
The debug circuits inside the OCD take up the available circuit surface area on the microcomputer. The debugging function is also relatively weak compared to full ICE because some terminals cannot be debugged, the debugging can be performed at high speed. Moreover, there is little difference between debugging and actual operation so that OCD is ideal for final debugging and parameter adjustment on the actual device.
Due to these circumstances, OCD has become widely utilized in recent years since it offers the advantage that debugging can be performed while the microcomputer is still mounted on the target device. Many diverse types of debug I/F (hereafter called interface) are utilized with OCD but the JTAG I/F proposed by the JETAG (Joint European Test Action Group. (Currently JTAG) and based on the IEEE std. 1149.1-1990 “Standard Access Port and Boundary-Scan Architecture” created by the US Institute of Electrical and Electronic Engineers is often used. The JTAG I/F is a standard I/F and therefore offers advantages such as a small number of pins and easy creation of the emulator.
A debug system utilizing OCD is disclosed in JP 2002-366378 A. This debug system as shown in FIG. 12 (FIG. 1 of JP 2002-366378 A) contains a JTAG interface circuit 2 (JTAG I/F) between the target device and a host computer 1. On the target device, a microcomputer containing a Central Processing Unit (CPU) 8 and a memory 19 are installed on the target board 3. A debugger 4 is installed on the host computer. A JTAG debug module 5 serving as the dedicated debug circuit is installed on the CPU8. A parallel cable 6 connects the debugger 4 and the JTAG interface circuit 2. A wire 9 on the substrate, and the JTAG dedicated cable 7 connect the JTAG interface circuit 2 and the JTAG debug module 5.
To improve the debugging efficiency, communication must be performed in parallel between the JTAG interface circuit 2 and the host computer 1, and also between the JTAG interface circuit 2 and the target board 3. The JTAG interface circuit 2 can perform parallel communication with the JTAG debug module 5 and the debugger 4 by way of the JTAG dedicated cable 7 and the parallel cable 6.
The JTAG interface circuit 2 includes a host I/F circuit for communication and (communication) control of the debugger 4 in the host computer 1, and a JTAG controller for communication and (communication) control of the JTAG debug module 5 on the target board 3. The JTAG interface circuit 2 communicates with the JTAG debug module 5 on the JTAG interface communication system, and converts the host computer 1 communication system to JTAG interface communication system.
The JTAG controller is normally a dedicated circuit and in most cases is made up of a Field Programmable Gate Array (FPGA) or gate arrays. The FPGA and gate arrays are high-priced and therefore have the problem that the OCD itself is also expensive.
To resolve the aforementioned problems, a method was contrived for using an inexpensive general-purpose microcomputer to perform certain JTAG controller functions or more specifically, control functions. In this method, the general-purpose microcomputer makes up a section of the JTAG controller so a FGPA is not used in that section. The cost of the JTAG controller can therefore be lowered, and consequently the OCD itself can also be inexpensively made.
However in the present times where companies are striving to reduce costs as much as possible, demands are being made to reduce the OCD cost even further. Executing all the JTAG controller functions on a general-purpose microcomputer is preferable for lowering the cost even more than in the above methods. Using a general-purpose microcomputer instead of the JTAG controller would eliminate the need for a high-priced device such as an FGPA and therefore lower the OCD cost even further.
Besides the control section however, the JTAG controller also contains a parallel target I/F circuit for transmitting data in parallel to and from the microcomputer on the target board.
The present inventor has recognized that there is no inexpensive general-purpose microcomputer containing an internal parallel I/F circuit and so a high-priced microcomputer containing a parallel I/F circuit serving as the target I/F circuit must be utilized making it impossible to reduce the cost.